RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

In contrast to most ISAs, the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open architecture ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which avoids a usual weakness of new instruction sets. The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without over-architecting for a particular micro architecture style.

Goals in defining RISC-V

  • A completely open ISA that is freely available to academia and industry.
  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.
  • An ISA that avoids over-architecting" for a particular micro-architecture style (e.g.,micro-coded, in-order, decoupled, out-of-order) or implementation technology (e.g.,full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.
  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.
  • Support for the revised 2008 IEEE-754 floating-point standard.
  • Both 32-bit and 64-bit address space variants for applications, operating system kernels, and hardware implementations.
  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.
  • A fully virtualizable ISA to ease hypervisor development.
  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA design.
S.No Instruction Formats Availability
1 RV32I Immediate
2 RV32IM Immediate
3 RV32IMF Immediate
4 RV32IMFD Under Development
5 RV32IMFA Immediate
6 RV64I On Demand
7 RV64IM On Demand
8 RV64IMFA On Demand
9 RV64IMF On Demand
10 RV64IMFD On Demand