MIPI CSI-2 (Camera Serial Interface) Transmitter IP defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. The MIPI CSI-2 Transmitter IP provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
Features
Compliance as per MIPI-CSI-2 version3.0
Compliance with C-PHY 2.0 for MIPI CSI-2 Version3.0
Compliance with D-PHY 2.5 for MIPI CSI-2 Version3.0
Compatibility with I2C and I3C(SDR,DDR) for CCI interface
CSI-2 Transmitter supports Pixel to Byte conversion from Application layer to LLP
layer
CSI-2 Transmitter should support continuous clock behavior in clock lane when
implemented in D-PHY physical layer
CSI-2 Transmitter provides the de-skew sequence pattern in Data Lane Module.
CSI-2 Transmitter supports Lane Distribution Function which accepts a sequence of
packet bytes from Low Level Protocol and distributes them across N-Lanes where each
lane is independent of PHY layer
CSI-2 Transmitter supports sync word insertion through PPI command while operating in
C-PHY physical layer
CSI-2 Transmitter will insert the Filler bytes in LLP layer in conjunction with C-PHY
physical layer to ensure that packet footer ends with 16-bit word boundary
CSI-2 Transmitter will set the 24 and 25 bit of packet header to be zero
CSI-2 Transmitter defines the minimum time for the frame blanking period
CSI-2 Transmitter is used to select the starting seed in scrambler and de-scrambler by
Sync word
Data Format supported are:
YUV (422)
RGB (888/565)
RAW (8/10)
Generic 8-bit long Packet data type
User defined byte based data
CSI-2 Transmitter supports C-PHY/D-PHY/A-PHY/M-PHY. Only one PHY layer can be
configured at a time of transmission
Processor Interfaces are AHB-Lite/ APB/ AXI for configuration
Supports 16 Virtual channels for D-PHY and 32 Virtual channels for C-PHY
