VLSI Digital Design flow comprises two basic phases: Logic Design and Verification. This course would cover theoretical and practical implementation of digital design and verification. Aim of course is covering the important problems/algorithms/tools, so that students get a comprehensive idea of the whole digital VLSI design flow with main focus on verification.
VLSI (Very Large Scale Integration) design has undergone a dramatic improvements in performance while achieving reduction in the size, cost and power consumption. Complexity in such systems arises as the number of discrete components that have to be integrated into a single chip which were designed separately and using different tools and flows. Thus verification phase forms the 70% of life-cycle of VLSI product.
VLSI Design and Verification (DV-500) provides training in design and verifying complex VLSI digital systems. Emphasis of the teaching curriculum is on design and Universal Verification Methodology (UVM) with practical applications. The curriculum has been designed in consultation with industry and academic experts and our strategic partners, to map the skill sets and methodologies, which is high in demand in VLSI verification industries.
This course is frequently updated in synchronization with the industry to provide the trainees in-depth knowledge and skills required by VLSI verification field around the globe.
It provides comprehensive understanding about the fundamental principles, methodologies and industry practices. This uniquely training makes the successful participants readily employable in multiple roles available in broad spectrum of relevant industries.
B.E/ B.Tech/ B.Sc/ MSc/M.E/M.Tech in Electronics Stream
