S.NO |
Feature |
3-Wire SPI |
4-Wire SPI |
|---|---|---|---|
Data Lines |
Single bidirectional SDIO (half- duplex) |
Separate MOSI (master slave)→ and MISO (slave master) for full-→ duplex |
|
Total Wires |
3: SCLK, SS/CS, SDIO | 4: SCLK, SS/CS, MOSI, MISO | |
Communication Mode |
Half-duplex : Master/slave take turns on SDIO | Full-duplex : Simultaneous data transmission and reception | |
Throughput |
Lower (due to turnaround delays) |
Higher (no turnaround delays) |
|
Bus Contention Risk |
Possible if master/slave drive SDIO simultaneously |
Minimal (MOSI/MISO are independent) |
|
Pin Usage |
Saves 1 pin (ideal for low-pin- count systems) |
Requires more pins but simplifies timing |
|
Turnaround Phase |
Required (delay between master slave and slave master→ → phases) |
Not required (MOSI/MISO operate independently) |
|
Example Transaction |
|
Master sends command on MOSI while slave responds on MISO simultaneously |
|
Clock Modes (CPOL/CPHA) |
Same as 4-wire SPI (4 modes based on clock polarity and phase) |
Same as 4-wire SPI (4 modes based on clock polarity and phase) |
|
Use Cases |
Sensors,EEPROMs, pin- constrained systems |
High-speed ADCs/DACs, displays, full-duplex systems |