SPI Intro

Serial Peripheral Interface (SPI) is a synchronous serial communication protocol widely used in embedded systems for high-speed data exchange between microcontrollers and peripheral devices. However, in the 3-wire SPI interface, the data transmission occurs in half-duplex mode, where the same data line is used for both transmission and reception

FEATURES

  • Operating range 1 MHz to 20 MHz of SPI clock speed
  • Memory space and Register space access is supported
  • Data is driven based on spi_mode, config through APB/UART/AXI/AHBL interface.

Serial Peripheral Interface (SPI)

SPI in 3-wire mode requires the following signals:

  • SCLK (Serial Clock): Generated by the master to synchronize data transfer
  • SS/CS (Slave Select/Chip Select): Activated by the master to enable communication with a specific slave
  • SDIO (Serial Data Input/Output): Bidirectional line for half-duplex data exchange

Working Principle

  • The master generates the clock signal (SCLK) and controls communication
  • Data transmission occurs bit-by-bit over the single SDIO line, requiring direction control
  • Slave selection is managed through the SS/CS line: When SS is low, the corresponding slave is active; other slaves remain inactive
  • Since MOSI and MISO are combined into one line, SPI 3-wire operates in half-duplex mode, meaning data transmission and reception cannot happen simultaneously
  • The master and slave share the SDIO line but take turns transmitting data
  • The master initiates communication by pulling SS low and generating SCLK
  • Master-to-Slave communication: The master sends data on SDIO during the first set of clock cycles
  • Slave-to-Master communication: The master stops driving SDIO (enters high-impedance mode), and the slave responds by transmitting data on the same SDIO line during subsequent clock cycles

SPI Modes of Operation

SPI has four different modes, determined by the clock polarity (CPOL) and clock phase (CPHA):

  1. Mode 0: CPOL = 0, CPHA = 0 (Clock idle low, data sampled on rising edge)
  2. Mode 1: CPOL = 0, CPHA = 1 (Clock idle low, data sampled on falling edge)
  3. Mode 2: CPOL = 1, CPHA = 0 (Clock idle high, data sampled on falling edge)
  4. Mode 3: CPOL = 1, CPHA = 1 (Clock idle high, data sampled on rising edge)

Advantages

  • Fewer Pins Required
  • Reduces Wiring Complexity
  • Simplifies Large-Scale Systems

Applications of SPI

  • Embedded Systems & Microcontrollers
  • Memory Devices
  • Display Interfaces
  • ADCs & DACs
  • Communication Modules
  • Industrial Applications
  • Secure Cryptographic Modules
  • Automotive Applications
  • FPGA & ASIC Communication
  • Audio Codecs

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